This invention relates generally to simulation systems and more particularly to a method and apparatus for simulating a storage component.
Software simulation tools are used on a regular basis by circuit designers to to test and to verify the functionality of their circuits. With a software simulation tool, a designer defines a circuit using a definitional language, such as Verilog XL. This definition includes a specification of the components in the circuit, as well as the connections between the various components. Once the circuit is defined, the designer invokes the simulation engine of the tool to interpret the definition of the circuit provided by the designer, and to simulate the behavior of the circuit to provide to the designer a set of results. Thereafter, it is up to the designer to determine, based upon the results, whether the circuit worked as he intended. The major advantage of using a software simulation tool is that it enables a circuit design to be tested without ever having to physically build the circuit. By not building the circuit, a significant amount of time and resources is often saved. With simulation tools, the results are only as good as the models used to represent the circuit components. If the models are flawed, the results will also be flawed. Because of this, it is imperative that the components be modeled accurately.
One type of component that appears frequently in circuits, and hence is simulated frequently, is that of a storage component. As used herein, the term storage component refers to any component that is capable of storing one or more bits of data, including a flip-flop, a latch, a register, etc. Unlike combinational logic components (such as AND gates and OR gates), a storage component may have some stringent timing requirements that must be met in order to operate properly. For example, there may be a certain amount of setup time that is required before the application of a data signal in order for the data signal to be stored in the storage component. There may also be a certain hold time during which a signal must be maintained in order for the storage component to perform the desired function. These timing requirements, referred to as setup and hold times, are checked by the simulation engine of the simulation tool to determine whether there are any timing violations in the circuit. If a timing violation is detected, the simulation engine provides an indication of the timing violation, thereby notifying the designer that there may be an error in the circuit. These timing requirement checks are important in all circuits, but they are especially important in circuits having both synchronous and asynchronous components. With asynchronous components, events can occur at any time. Because of the unpredictability of the timing of events, some of the timing requirements of the storage components may not be met. If timing violations result from the interaction between the synchronous and asynchronous components, the designer should be alerted. Under the current storage component model, if a timing violation occurs for a storage component, the storage component outputs an x, indicating that due to the timing violation, the output of the storage component is uncertain. This x output serves two purposes. First, it indicates the true state of affairs. Because of the timing violation, it is truly not known whether the output of the storage component is a logical 1 or a logical 0. Second, the x output provides an indication to the designer that a timing violation has occurred. This serves to alert the designer to the presence of the timing violation.
In theory, the use of the x output is sound. In practice, however, the x output may lead to unusable results. To elaborate, whenever a circuit component, whether it be a combinational logic component or another type of component, experiences an x at one of its inputs, it will provide an x at its output. This makes logical sense because if an input is uncertain, the output is also uncertain. Given this rule, if a storage component outputs an x in response to a timing violation, it will cause whatever components that receive the x as input to also output an x. In turn, any components that receive the x outputs from those components will also output an x, and any components that receive the x outputs from those other components will also output an x, and so on. This process of propagating the x, referred to as fanout, continues until all components that depend directly or indirectly upon the output of the storage component have received and propagated the x. If the number of components that depend upon the output of the storage component is large, the fanout can be quite substantial, and if the fanout is substantial, the designer will receive from the simulation engine a set of results having a large number of x""s. X""s, because they represent uncertainty, provide very little information as to the operation of the circuit. With x""s as the outputs, the designer cannot determine whether the circuit operated properly. Hence, such results are almost useless to the designer.
As this discussion shows, the current model for storage components can lead to useless simulation results. Since such results are clearly undesirable, an improved mechanism for simulating storage components is needed.
In light of the shortcomings of the prior art, the present invention provides an improved mechanism for simulating storage components. The present invention is based, at least partially, upon the observation that while it is necessary for a storage component to provide an x at its output to indicate a timing violation, it is not necessary for the component to maintain the x indefinitely. Rather, after a certain number of timing units, the x may be changed to a certain value, such as a logical 1 or a logical 0. By changing the x to a certain value, the present invention makes it possible to meaningfully test the rest of the circuit even when a timing violation is experienced by a storage component.
In accordance with this observation, the present invention simulates the behavior of a storage component as follows. First, a determination is made as to whether a timing violation has occurred for the storage component. This determination is made by the simulation engine by checking the timing requirements specified in the model of the storage component. If one or more timing violations is detected, then an x is reflected at the output of the storage component. This x is maintained at the output of the storage component for a predetermined number of timing units. The simulation engine, recognizing the x as an indication of uncertainty, causes an indication of error to be provided to the designer. The timing violation is thus manifested to the designer.
After the predetermined number of timing units has expired, however, the output of the storage component is changed from x to a certain value, such as a logical 1 or a logical 0. For purposes of the present invention, which value the x is changed to is not that important. What is important is that it is changed to a value that is certain. By changing the output to a certain value, the present invention prevents the x at the output of the storage component from indefinitely propagating to other components in the circuit. This in turn prevents large numbers of x""s from appearing in the results provided by the simulation engine to the designer. Instead, values that are certain will appear in the results. Because these values are certain, they can be used by the designer to determine whether the rest of the circuit operated properly.
The present invention provides the best of both worlds. On the one hand, it provides an x at the output of the storage component to enable the simulation engine to manifest a timing violation to the designer. On the other hand, it prevents the x from indefinitely propagating to other components in the circuit, thereby enabling the rest of the circuit to be meaningfully tested. Because it performs the notification function without sacrificing the testing function, and vice versa, the present invention provides a complete solution to the problem posed above.